1. Field of the Invention
The present invention relates to the field of automatic circuit extraction and verification within a computer system. More specifically, the present invention relates to the field of circuit extraction and simulation for application within a computer controlled electronic design automation (EDA) system.
2. Related Art
The IEEE standard 1149.1, IEEE Standard Test Access Port and Boundary-Scan Architecture, IEEE Standard 1149.1-1990 (including IEEE Standard 1149. 1a-1993), published by IEEE, is a set of rules that define a boundary-scan and test access architecture for integrated circuit designs. The boundary-scan technique puts a shift-register stage (contained in a boundary-scan cell) beside each component pin so that signals at component boundaries can be controlled and observed using scan principles. The test access architecture incorporates design-for-test features like internal-scan paths, BIST (Built In Self-Test) and other support functions.
IEEE Standard 1149.1-1990 (including IEEE Standard 1149.1a-1993) is a set of 192 rules, 49 permissions and 16 recommendations in 12 chapters and 135 description pages. Almost 85% of the rules constrain the functional behavior of the boundary-scan and test access circuitry under different conditions. The remaining 15% of the rules constrain the dedication and isolation of boundary-scan circuitry. BSDL, as defined in the supplement to IEEE Standard 1149.1-1990 & IEEE Standard 1149.1a-1993, IEEE Standard Test Access Port and Boundary-Scan Architecture, published by IEEE, is a subset and standard practice of VHDL (IEEE Standard 1076-1993) that describes the testability features of components that comply to IEEE Standard 1149.1. Integrated circuit (IC), board and system test tools use BSDL to characterize IEEE Standard 1149.1-compliant designs.
It is estimated that about 75% of boundary-scan ICs have hand-generated or macro-cell based boundary-scan circuitry. It is relatively easy to implement the 15% of IEEE Standard 1149.1 rules that constrain the isolation and dedication of boundary-scan circuitry, as the generation of system and boundary-scan logic can be carried out as two separate activities. However, it is not easy to hand-generate circuitry that is in full compliance with the 85% of rules that constrain functional behavior as they require the integration of system and boundary-scan circuitry. Designers can synthesize boundary-scan circuitry at the RTL following "correct-by-construction" design rules, see Robinson M. F., Mailhot F., Konsevich J., "Technology independent Boundary-Scan synthesis", International Test Conference 1993, pp 157-166. Optimization and scan or BIST insertion can introduce compliance problems.
A non-compliant boundary-scan IC may damage itself or other ICs if it can not be isolated. Integrity, interconnect and cluster tests may fail or produce misleading results. Time and test coverage can be lost working around. When boundary-scan design is done by hand, the BSDL description is also hand generated and prone to defects, see Parker, K. P., The Boundary-Scan Handbook, Kluwer Academic Press, 1992, chapter 5, section 5.1.10. Even for synthesized boundary-scan designs, the system generated BSDL description may not be valid, unless the design is verified for compliance to IEEE Standard 1149.1.
Defective BSDL descriptions can get caught when the BSDL is parsed for syntactic and semantic correctness during test generation. Subtle defects may only cause failures on the tester or ATE (Automatic Test Equipment). Such failures may originate in one of several BSDL files or be caused by a real physical defect. It can become quite expensive to diagnose and resolve such problems. It would be advantageous to provide a computer implemented automatic method for checking design conformance to IEEE Standard 1149.1 and generating correct BSDL descriptions.
Commercially available boundary-scan tool suites generate a set of functional test vectors for the target boundary-scan logic using well-documented strategies. In Dahbura A. T., YAU C. W., Uyar M. U., "An optimal test sequence for JTAG boundary-scan controller", International Test Conference 1989, pp 55-62, a technique is proposed that generates EQU K+k.sub.1 N.sub.bs +k.sub.2 N.sub.ir +k.sub.3 N.sub.id
vectors, where k, k.sub.1, k.sub.2, and k.sub.3 are constants. N.sub.bs denotes number of boundary scan register (BSR) cells. N.sub.ir denotes the number of DIR (Device Identification Register) bits. This approach generates a considerable number of vectors. It only verifies the TAP controller exhaustively and the coverage of test data registers is not complete.
In Raymond D. W., Wedge D. E., Stringer P. J., Harold W. N., Suzanne T. J., Craig T. P., Windsor S., "Algorithmic Extraction of BSDL from 1149.1-compliant Sample ICS", International Test Conference 1995, pp 561-568, it is proposed to extract BSDL from IEEE Standard 1149.1-compliant ICs by simulating the design using hardware and software. However, the BSDL generated is not complete because it includes only the three mandatory instructions (EXTEST, BYPASS and SAMPLE/PRELOAD) and if possible IDCODE. Other instructions (HIGHZ, CLAMP, INTEST or RUNBIST) are not found at all. Moreover, it is not possible to find them using the technique described by Raymond. Further, none of the above techniques offer mechanisms for reducing the exhaustive instruction opcode search processing required for large instruction register bit sizes.
Accordingly, the present invention provides a computer implemented method and system for performing extraction and compliance checking of an IEEE 1149.1 standard circuit. The TAP controller is extracted using an efficient process and then its states are verified. The boundary scan register cells and their primary inputs and primary outputs are characterized. An exhaustive TDR (test data register) check is performed and all supported instructions are extracted (if present) and checked for compliance. The present invention provides novel processes for reducing time required for locating instruction opcodes for designs having large bit sized instruction registers. These and other advantages of the present invention not specifically mentioned above will become clear within discussions of the present invention presented herein.